Our proposed method adopts motion compensated
frame interpolation (MCFI). The purpose of the
proposed method is to insert one or several
interpolated frames between any two contiguous
original frames with motion compensation. Hence,
the first and most important part of this
processing is to find true motion. True motion
would be found by the procedure with motion
estimation, motion classification, and motion
correction or by processing motion vector field
from bitstream with classification, assignment,
and correction. There are several techniques in
our proposed procedure for motion re-estimation,
including bi-directional motion vector
searching, multi-directional enlarged matching,
border motion vector searching, and multi-grid
motion vector classification. These techniques
need to refer to spatial information and
temporal information so as to find some motion
vector candidates for true motion vector
selecting. Motion vector selector would choose a
best motion vector for compensation under some
pre-defined condition and neighboring motion
vector information.
2. Integrated Architecture Design for Overlap
Smoothing and In-loop Deblocking in VC-1
We presents several novel processing methods and
an efficient integrated architecture for VC-1
deblock filtering. These proposed methods and
architecture are based on a special basic block
named overlapped block. In order to increase the
performance and decease the processing time, we
integrate overlap smoothing with in-loop deblock
filtering. We also pipeline the procedure with
block reconstructing even though the filtering
procedure is frame-based in VC-1 standard. For
efficiently utilizing system resources, we
elaborately propose two other unique methods,
multiple processing order and modified chroma
processing order. Moreover, an integrated
architecture is well-designed, implemented in
VHDL, and synthesized by TSMC 0.18-.m
technology on Artisan cell library. The
specification supports Advanced Profile with the
level up to 4.1, and this architecture has
capability to deal with HDTV1080p (1920x1080) 30
fps video and HDTV 2048x1536 24 fps video at 200
MHz. Besides, for many deblocking filter for
video post-processing with a similar processing
order, we also can apply our proposed methods to
efficiently implement the architecture.
